1. Field of the Invention
The present invention relates to a device for generating addresses which generates addresses when accessing a memory device in a data processing device, and, in particular, to a device for generating structured addresses wherein a plurality of data items with the same data configuration such as control data for a communication line is stored in a memory device, so that addresses can be conveniently calculated when processing these data items by a same program.
2. Description of the Prior Art
In a communication device for controlling a plurality of communication lines such as communication networks, data for managing the state of the individual communication lines exists independently, but there are many cases where a homogeneous data structure is adopted to format this data for easy programming.
An example of this type of data structure is shown in FIG. 1. In the data structure in this figure, it is possible to determine a specific communication line by combining three types of data items--the physical address and the logical port number of the remote station, and the logical port number of the local station. To detect duplicating and truncating of data or the like, when transmitting or receiving data using this communication line the transferred/received data is controlled by providing respective sequence numbers. In addition, this data has an inherent value for each communication line, and has the characteristic that the data structure is the same.
For programming using this data structure, it is possible to specifically set data as a base address for the managed data and use an offsetting technique.
For such a purpose, an Intel 18086 processor for example, where a memory device is accessed through physical (hardware) calculations by adding a direct value showing an offset, or a register value to a register indicating a base address.
With this type of conventional general purpose processor, i.e. the Intel 18086, this addressing mode is used to expand address space, and an arithmetic operations unit or a computing element with enough bits to cover the total address range is used. For this reason, there is the problem that the time required for the Calculations is one clock cycle at least and, as a result, data access is slow.
Also, in the Application Specific Integrated Circuit (ASIC) technique in which circuits which implement peripheral devices, and specialized processors are provided on a semiconductor substrate, the above-mentioned type of computing element dedicated to address calculation cannot be provided in order to minimize the amount of hardware, and the data computing element must serve double duty. In this case, the calculations are made by the program, whenever the data is accessed, and the offset must be added to the base address. The number of steps is therefore increased and the execution time is also increased. Elimination of these drawbacks is therefore desired. In addition, in a processor which uses a. microcode, the execution time for calculating addresses in the microcode cannot be reduced even though the number of steps is reduced in the program used.
Furthermore, when access is made with an incorrect offset caused by an error in the program, a different data structure is accessed, and, as a result it frequently occurs that data is destroyed during program development. Unexpected destruction of data address makes debugging difficult, and therefore a program which restricts the range of addresses accessed is desirable. However, with conventional addressing, the range of physical addresses is increased because the total address range indicated by the offset address on the base address as standard is effective, and it is difficult to limit incorrect addresses by hardware means. Accordingly, in order to access this type of specific data structure, the program must check address addition and range, which increases the processing time with a conventional processor.
As outlined above, conventionally, a computing element with enough bits to cover the total address range is used, and the time required for the calculations is at a minimum, one clock cycle, and as a result data accessing is slow. Additional problems are that, even in the case where the computing element serves double duty, the number of steps is increased and the execution time is also increased in the calculations by the program. A further problem is that even in a processor which uses a microcode, although the number of steps is reduced in each program used, the execution time for calculating addresses in the microcode cannot be reduced. Further, it is difficult to limit incorrect addresses by hardware means, and in order to access this type of specific data structure, the program must check address addition and range, which increases the processing time.